Western Electric 1A  
Written by Accutron on 2017-11-25  

Introduced in the June 1965 edition of the Bell Laboratories Record, the Western Electric 1A memory card is a permanent magnet twistor ROM for the Bell #1 Electronic Switching System (1ESS). Developed by Bell Labs in 1957, twistor is a magnetic memory similar in principle to traditional magnetic core memory, but designed to address the manufacturing problems inherent to core memory construction. Instead of storing bit values on individually hand-wired magnetic cores, twistor stores bits on a permalloy tape, wound in a 45-degree helix around a 3 mil copper wire which serves as the functional equivalent of a core memory's X line. Solenoids wrapped around groups of twistor wires serve the same function a core memory's Y line. To complete an entire cube of twistor memory, the twistor wires and solenoid wires are laminated into separate sheets, which are oriented 90 degrees apart and folded repeatedly over each other, in much the same fashion as an origami paper spring.

By inserting the solenoid loops between twistor folds instead of around them, and replacing one half of each solenoid loop with an array of permanent magnets, twistor functions as a permanent store. The 1A and companion 2A memory cards are just such an array, consisting of a 64x44 grid of tiny vicalloy bar magnets fused to an aluminum card. Each twistor store consists of 16 modules of 128 cards each, for a total of 131,072 44-bit words or 704kB. An ESS central office would include between two and six twistor stores.

Twistor was a narrowly adopted technology, used in only a handful of Western Electric-manufactured systems. In addition to the 1ESS, twistor memory was used in the Bell/UNIVAC Target Intercept Computer developed for the Nike Zeus antiballistic missile system, and the Traffic Service Position System (TSPS), introduced in 1969 to replace conventional cord switchboards.


Western Electric 1A Memory Card, a permanent magnet twistor ROM.


1A card, enlargement of vicalloy permanent magnets.

This article is part of the [Logic & Memory Circuits] exhibit.

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